T/ZGTXXH 096-2024 Core-Chip Interconnection Interface Specification

Scope

Main technical content: This standard conducts in-depth research and extensively solicits professional needs and suggestions from domestic chip design manufacturers, packaging manufacturers, intellectual property (IP) suppliers, and enterprises engaged in various technical applications. It formulates an interconnect interface standard suitable for multi-chiplets operating at high speeds of 32Gbps and above, defining the following aspects: 1. An interconnect solution based on differential serial signals, which enhances the stability and reliability of signal transmission; 2. By integrating domestic packaging processes, it optimizes packaging friendliness and significantly reduces packaging costs; 3. It proposes Lane crossing and polarity reversal features, making packaging more flexible; 4. It simplifies the link establishment and initialization processes, lowering application thresholds and software costs; 5. It defines comprehensive testability design and error retransmission mechanisms, improving the high packaging yield and transmission reliability of domestic products; 6. It proposes a backpressure mechanism based on retransmission, enhancing the overall robustness of the system.

Development Information

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