T/CASAS 016-2022 Active
T/CASAS 016-2022 The transient double-interface testing method for the thermal resistance of the junction and housing of silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs) is provided
Abstract
Scope: This document specifies the transient double-interface test method for the junction thermal resistance of silicon carbide metal oxide semiconductor field-effect transistors (SiC MOSFETs). This document is only applicable to the junction thermal resistance test of SiC MOSFET discrete devices, where the voltage V_sd between the source and drain is used as the temperature-sensitive test parameter. Main technical content: Silicon carbide metal oxide semiconductor field-effect transistors (SiC MOSFETs) are gradually being widely used in fields such as radar detection, medical communication, transportation, and new energy due to their advantages including a wide bandgap, high critical breakdown electric field strength, and excellent high-temperature resistance. The junction thermal resistance, as an important parameter characterizing the heat transfer capability in the heat conduction path, is one of the key technical indicators directly reflecting the device's thermal performance and can provide reference for the thermal design and optimization improvement of the device. Therefore, accurate thermal resistance testing is of great significance for the identification, evaluation, and application of SiC MOSFETs.
General Product Information
| Document Type | Group standards |
|---|---|
| Standard Status | Active |
| Standard Code | T/CASAS 016-2022 |
| ICS | Integrated Components of Semiconductor Devices |
| Implement Date | 2022-07-18 |