T/SIOT 601-2018 Specification for Lightweight Operating Systems of Smart Hardware - System Architecture

Scope

Scope: This standard specifies the system architecture terminology and definitions, system structure, and hierarchical model and inter-layer relationships in intelligent hardware lightweight operating systems. This standard applies to the system architecture design, development, and implementation of intelligent hardware operating systems, and can be used as a basis for enterprises to select or evaluate intelligent hardware operating systems. The users of this standard include independent software testing institutions, organizations developing intelligent hardware-related software products, implementation and consulting service agencies, etc. Other fields related to the application development of intelligent hardware lightweight operating systems can also refer to and use this standard. Main technical content: This standard specifies the system architecture specifications of intelligent hardware lightweight operating systems, including: system architecture terminology and definitions, system structure, and hierarchical model and inter-layer relationships. The system architecture should be designed with a layered structure, and it must meet the following requirements: the functional definitions between layers are independent of each other, and the system functions can be called using the interfaces of each layer. The system architecture design should support technicians to develop collaboratively according to the division of labor by layers. Among them, the system interface provides two sets, namely: a) the hardware abstraction layer functional interface facing the lower layer: HAL API, which supports the portability of system software on different hardware platforms; b) the system functional interface facing the upper layer application: OS API, which supports applications to call system functions through these interfaces. At the same time, it is recommended that intelligent hardware operating systems should include six layers: hardware abstraction layer, syste

Development Information

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