GB/T 33657-2017 Active National standards

GB/T 33657-2017 Nanotechnologies—Electrical operating parameter test specification of wafer level nano-scale phase change memory cells

GB/T 33657-2017 Nanotechnologies—Electrical operating parameter test specification of wafer level nano-scale phase change memory cells

Publish Date: 2017-05-12 Implement Date: 2017-12-01 For services related to genuine standard inquiry, procurement, translation, and other related services in China, please Contact Us

Basic Information

Standard Code: GB/T 33657-2017
Standard Type: National standards
Standard Status: Active
is_force_gb: no
CCS Name: Semiconductor integrated circuits
ICS Name: Integrated circuits, microelectronics
Publish Date: 2017-05-12
Implement Date: 2017-12-01
Pages: 12 pages

Scope

This standard specifies the wafer test specifications for the read, write, and erase parameters of nanoscale phase-change memory cells. The test results can be used to characterize the electrical operability of phase-change memory materials or devices. This standard applies to phase-change memory cells with electrode dimensions smaller than 100 nm, which are manufactured using semiconductor wafer processing based on chalcogenide compounds as the main raw materials. Phase-change memory cells with dimensions between 100 nm and 300 nm can also be tested according to this standard. This standard does not apply to memory cells that include peripheral drive circuits.

Development Information

Word Count: 16 Thousand words Pages: 12 pages

Referenced Standards

Related Standards

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