DZ/T 0101.12-1994
Active
SJ 21451-2018
Active
Industry standards-Electronics
SJ 21451-2018 Integrated circuit ceramic package-Technical requirement for wafer-sawing process
SJ 21451-2018 Integrated circuit ceramic package-Technical requirement for wafer-sawing process
Price:
$ 30
Basic Information
Standard Code:
SJ 21451-2018
Standard Type:
Industry standards
Standard Status:
Active
is_force_gb:
no
CCS Name:
-
ICS Name:
-
Publish Date:
2018-01-18
Implement Date:
2018-05-01
Pages:
9 pages
Scope
This standard specifies the general requirements for the dicing process of military integrated circuits, as well as the detailed requirements for the raw materials, equipment, process flow, key control points, and inspections used in the dicing process. This standard applies to the dicing process of 12-inch and smaller-sized integrated circuit silicon wafers (excluding wafers with bumps) (hereinafter referred to as the dicing process).
Development Information
Referenced Standards
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