GB/T 45721.1-2025 Active National standards

GB/T 45721.1-2025 Semiconductor devices—Stress migration test—Part 1:Copper stress migration test

Publish Date: 2025-05-30 Implement Date: 2025-09-01 For services related to genuine standard inquiry, procurement, translation, and other related services in China, please Contact Us

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Basic Information

Standard Code: GB/T 45721.1-2025

Standard Type: National standards

Standard Status: Active

is_force_gb: no

CCS Name: Semiconductor discrete devices

ICS Name: Integrated Components of Semiconductor Devices

Publish Date: 2025-05-30

Implement Date: 2025-09-01

Pages: 28 pages

Scope

This document specifies a constant-temperature aging method used to test the sensitivity of copper (Cu) metallization structures on microelectronic wafers to stress-induced voids (SIVs). This method will primarily be used in the wafer-level process development of products, and the results will be applied to lifetime prediction and failure analysis. In some cases, this method can be applied to packaging-level testing. However, due to the long testing time, this method is not suitable for batch delivery inspections of products. Double Damascus copper metallization systems typically have linings, such as tantalum (Ta) or tantalum nitride (TaN), at the bottom and sides of the trenches etched into the dielectric layer. Therefore, for structures with a single through-hole contacting a wide line below, a resistance drift caused by voids below the through-hole will instantly lead to an open-circuit failure when it reaches a certain percentage specified by the failure criterion.