GB/T 44791-2024 Active National standards

GB/T 44791-2024 Integrated circuit 3D packaging—Requirement for bumping-wafer-thining process and evaluation

GB/T 44791-2024 Integrated circuit 3D packaging—Requirement for bumping-wafer-thining process and evaluation

Publish Date: 2024-10-26 Implement Date: 2025-05-01 For services related to genuine standard inquiry, procurement, translation, and other related services in China, please Contact Us
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Basic Information

Standard Code: GB/T 44791-2024
Standard Type: National standards
Standard Status: Active
is_force_gb: no
CCS Name: Microcircuit
ICS Name: Integrated circuits, microelectronics
Publish Date: 2024-10-26
Implement Date: 2025-05-01
Pages: 16 pages

Scope

This document specifies the thinning process and evaluation requirements for three-dimensional packaging of integrated circuits with bumped wafers of sizes up to and including 12 inches (hereinafter referred to as the thinning process).
Note: 1 inch = 2.54 cm.

Development Information

Word Count: 21 Thousand words Pages: 16 pages

Referenced Standards

Related Standards

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