GB/T 43536.2-2023 Active National standards

GB/T 43536.2-2023 Three dimensional integrated circuits—Part 2:Alignment of stacked dies having fine pitch interconnect

GB/T 43536.2-2023 Three dimensional integrated circuits—Part 2:Alignment of stacked dies having fine pitch interconnect

Publish Date: 2023-12-28 Implement Date: 2024-04-01 For services related to genuine standard inquiry, procurement, translation, and other related services in China, please Contact Us

Basic Information

Standard Code: GB/T 43536.2-2023
Standard Type: National standards
Standard Status: Active
is_force_gb: no
CCS Name: Semiconductor integrated circuits
ICS Name: Integrated circuits, microelectronics
Publish Date: 2023-12-28
Implement Date: 2024-04-01
Pages: 12 pages

Scope

This document specifies the requirements for initial calibration and calibration maintenance between multiple stacked integrated circuits during the chip bonding process. It defines calibration marks and operational steps. This document is only applicable to inter-chip calibration using the electrical coupling method.

Development Information

Word Count: 25 Thousand words Pages: 12 pages

Same series standard

Referenced Standards

IEC 63011-1

Adopt standards

IEC 63011-2:2018

Related Standards

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