GB/T 44796-2024 Active National standards

GB/T 44796-2024 Integrated circuit 3D packaging—Requirement for bumping-wafer-sawing process and evaluation

GB/T 44796-2024 Integrated circuit 3D packaging—Requirement for bumping-wafer-sawing process and evaluation

Publish Date: 2024-10-26 Implement Date: 2025-05-01 For services related to genuine standard inquiry, procurement, translation, and other related services in China, please Contact Us
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Basic Information

Standard Code: GB/T 44796-2024
Standard Type: National standards
Standard Status: Active
is_force_gb: no
CCS Name: Microcircuit
ICS Name: Integrated circuits, microelectronics
Publish Date: 2024-10-26
Implement Date: 2025-05-01
Pages: 16 pages

Scope

This document specifies the general requirements, detailed requirements, and evaluation requirements for the dicing process of three-dimensional packages with bumps for integrated circuits with a size of 12 inches or less (hereinafter referred to as the dicing process).
Note: 1 inch = 2.54 cm.
This document is applicable to the dicing process of three-dimensional packages with bumps for integrated circuits with a size of 12 inches or less.

Development Information

Word Count: 21 Thousand words Pages: 16 pages

Referenced Standards

Related Standards

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