T/IAWBS 008-2019 Method for Detecting Residual Stress in SiC Chips

Scope

Scope: This standard specifies the optical non-destructive testing method for internal residual stress in SiC wafers. This standard is applicable to SiC wafers with appropriate thickness, and those with a transmittance of more than 30% to test light in the visible light range of 400-700nm; Main technical content: In recent years, the third-generation semiconductor materials represented by silicon carbide (SiC) have attracted worldwide attention. Due to its advantages such as a wide bandgap, high breakdown electric field strength, high saturated electron mobility, high thermal conductivity, low dielectric constant, and strong radiation resistance, it can be widely used in new energy vehicles, rail transportation, smart grids, semiconductor lighting, next-generation mobile communications, consumer electronics, and other fields. It is regarded as a core technology supporting the development of industries such as energy, transportation, information, and defense. The global market capacity will reach tens of billions of U.S. dollars in the future, and it has become one of the key research directions in the semiconductor industry of the United States, Europe, and Japan. Similar to traditional silicon-based wafers, residual stress is also generated during the manufacturing process of SiC wafers. Excessive residual stress not only causes failures such as warping and breaking of wafers, but also affects the electrical performance of SiC wafers due to the piezoresistive effect. Therefore, accurately measuring the residual stress of SiC wafers during the manufacturing process is of great significance for improving product yield and electrical performance.

Development Information

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