DZ/T 0101.12-1994
Active
SJ/Z 21357-2018
Active
Industry standards-Electronics
SJ/Z 21357-2018 Design guidelines for chip stacking process of SiP products
SJ/Z 21357-2018 Design guidelines for chip stacking process of SiP products
Price:
$ 30
Basic Information
Standard Code:
SJ/Z 21357-2018
Standard Type:
Industry standards
Standard Status:
Active
is_force_gb:
no
CCS Name:
-
ICS Name:
-
Publish Date:
2018-01-18
Implement Date:
2018-05-01
Pages:
11 pages
Scope
This guidance technical document specifies the general requirements for the design of the chip stacking process in system-level packaging (SiP) products, as well as detailed requirements for the structure, materials, and process design
Development Information
Referenced Standards
GB/T 12842-1991 Terminology for film integrated circuits and hybrid film integrated circuits
GB/T 14113-1993 Terminology of packages for semiconductor integrated circuits
GB/T 8750-2014 Gold bonding wire for semiconductor package
GB/T 9178-1988 Terminology for integrated circuits
YS/T 641-2007 Aluminium wire for semiconductor lead bonding
YS/T 678-2008 Copper wire for semiconductor lead bonding
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