GB/T 4937.29-2025 Semiconductor devices—Mechanical and climatic test methods—Part 29:Latch-up test
GB/T 4937.29-2025 Semiconductor devices—Mechanical and climatic test methods—Part 29:Latch-up test
Basic Information
Scope
This document describes the test method for current and overvoltage latching of integrated circuits.
This test is a destructive test.
The purpose of this test is to establish a method for judging the latching characteristics of integrated circuits and to define the failure criteria for latching. The latching characteristics are used to evaluate the reliability of the product and to reduce failures caused by latching, such as non-targeted failures (NTF) and electrostatic discharge (EOS) failures.
This test method is mainly applicable to complementary metal-oxide-semiconductor (CMOS) devices. If it is applied to other process technologies, the applicability needs to be confirmed separately.
The latching test is classified according to temperature in Section 4.1, and the failure level criteria are defined in Section 4.2.